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Parallel and Network-based Processing Research Group
Department of Electrical and Computer Engineering, University of Tehran
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Education

Research Experience

 Research Visits and International Collaborations

Courses

Publications

Book

1. M. Daneshtalab, M. Modarressi, Hardware Architectures for Deep Learning, IET publishers, UK, 2020.

(IET link)(Amazon link)

Book Chapters
1.    M. Modarressi, H Sarbazi-Azad, "Topology Specialization for Networks-on-Chip in the Dark Silicon Era", Chapter 4 of Advances in Computers: Dark Silicon and Future of On-chip Systems, Elsevier Advances in Computers, NJ, USA, 2018.
2.    M. Modarressi, H Sarbazi-Azad, "A Reconfigurable On-Chip Interconnection Network for Large Multicore Systems", Chapter 1 of Large-scale Network-centric Distributed Systems, John Wiley & Sons, NJ, USA, 2014. (Amazon Link) (Wiley Link)
3.    R. Jabbarvand, M. Modarressi, H. Sarbazi-Azad, "Fault-Tolerant Routing Algorithms in Networks on-Chip", Chapter 4 in Routing Algorithms in Networks-on-Chip, Springer, 2014. (Amazon Link) (Springer Link)
4.    M. Modarressi, H Sarbazi-Azad, "A High-Performance and Low-Power Reconfigurable Network-on-Chip Architecture", Chapter 13 of Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication, IGI Global Pubs, 2010. (Amazon link)
5.    R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, A novel de Bruijn based mesh topology for Networks-on-Chip, Chapter 16 in VLSI Design, IN-TECH Publishers, Austria, 2011,  ISBN 978-3-902613-50-9.
6.    R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, Shuffle-Exchange Mesh Topology for Networks-on-Chip, Chapter 5 in Parallel and Distributed Computing, IN-TECH Publishers, Austria, 2011, ISBN: 978-3-902613-45-5.

Journal Papers

1. H. Mahdiani, A. Khadem, A. Ghanbari, M. Modarressi, F. Fattahi-Bayat and M. Daneshtalab, "ΔNN: Power-Efficient Neural Network Acceleration Using Differential Weights," in IEEE Micro, vol. 40, no. 1, pp. 67-74, 1 Jan.-Feb. 2020.

2. S. H. Seyyedaghaei Rezaei, M. Modarressi, R. Ausavarungnirun, M. Sadrosadati, O. Mutlu, M. Daneshtalab, “NOM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories,”, in IEEE Computer Architecture Letters (IEEE CAL), 2020. (to appear)

3. Seyedolhosseini, A., Masoumi, N., Modarressi, M. and Karimian, N., “Daylight adaptive smart indoor lighting control method using artificial neural networks”, Elsevier Journal of Building Engineering, p.101141, 2019.

 4.    M. Bakhshalipour, P. Lotfi-Kamran, A. Mazloumi, M. Naderan-Tahan, M. Modarressi, and H. Sarbazi-Azad, “Fast Data Delivery for Many-Core Processors,” in IEEE Transactions on Computers (IEEE TC), 2018.

5.    M. Sadrosadati, A. Mirhosseini, M. Modarressi, H. Sarbazi-Azad, “BARAN: Bimodal Adaptive Reconfigurable-Allocator Network-on-Chip,” ACM Transactions on Parallel Computing, 2018.
6.    M. Keramati, M. Modarressi, and S. H. Seyedaghaei Rezaei. "Thermal management in 3d networks-on-chip using dynamic link sharing," Elsevier Microprocessors and Microsystems, vol. 52, pp. 69-79, 2017.
7.    R. Hojabrossadati, M. Modarressi, A. Yasoubi, M. Daneshtalab, and A. Khounsari. "Customizing Clos Network-on-Chip for Neural Networks." IEEE Transactions on Computers, vol. 66, no.11, 2017.
9.    A. Yasoubi, R. Hojabr, M. Modarressi, "Power-Efficient Accelerator Design for Neural Networks using Computation Reuse", in IEEE Computer Architecture Letters (IEEE CAL), vo. 16, no. 1, 2017.
10.    P. Mehrvarzy, M. Modarressi, H Sarbazi-Azad, "Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology", in Elsevier Journal of Microprocessors and Microsystems, 2016.
11.    P. Lotfi-kamran, M. Modarressi, H. Sarbazi-Azad, "An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors", in IEEE Transactions on Computers (IEEE TC), Sep. 2015.
12.    S. H. Seyyedaghaei, A. Mazloumi, M. Modarressi, P. Lotfi-Kamran, "Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip", in IEEE Computer Architecture Letters (IEEE CAL), Vo. 15, No. 1, Jun. 2016.
13.    M. Modarressi, H. Sarbazi-Azad, "Leveraging Dark Silicon to Optimize Networks-on-Chip Topology", in Springer Journal of Supercomputing, Vol. 71, No. 9, pp. 3549-3566, Sep. 2015.
14.    F.  Pakdamana, A. Mazloumia, M. Modarressi, "Integrated circuit-packet switching NoC with efficient circuit setup mechanism", in Springer Journal of Supercomputing, Vol. 71, No. 8, pp. 2787-2807, Aug. 2015.
15.    M. Modarressi, N. Teimouri, H. Sarbzai-Azad, "Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths", in Elsevier Integration, the VLSI Journal, Vol. 50, pp. 193-204, Jun. 2015.
16.    M. Modarressi, M. Asadinia, H. Sarbazi-Azad, "Using Task Migration to Improve Non-contiguous Processor Allocation in NoC-based CMPs", Elsevier Journal of System Architecture (JSA), Vol. 59, No. 7, Aug. 2013.
17.    M. Asadinia, M. Modarressi, H. Sarbazi-Azad, "New Non-contiguous Processor Allocation Algorithm in Mesh-based CMPs Using Virtual Point-to-point Links", in IET Computers and Digital Techniques (IET-CDT),  Vol. 6, No. 5, Sept. 2012.
18.    R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, "The 2D digraph-based NoCs: attractive alternatives to the 2D mesh NoCs", The Journal of Supercomputing, 59(1), pp. 1-21, 2012.
19.    R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, The 2D SEM: a novel high-performance and low-power mesh-based topology for networks-on-chip, International Journal of Parallel, Emergent, and Distributed Systems, Vol.25, No.4, pp.331-344, 2010.
20.    M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Application-Aware Topology Reconfiguration for On-Chip Networks", in IEEE Transactions on Very Large Scale Integrated Circuits (IEEE TVLSI), Vol. 19, No. 11, Nov. 2011.
21.    M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Virtual Point-to-Point Connections in NoCs", in IEEE Transactions on Computer-Aided Design for Integrated Circuits and Systems (IEEE TCAD), Vol. 29, No. 6, Jun. 2010.
Conference Papers
.    A. Firuzan, M. Modarressi, M. Daneshtalab, M. Reshadi, “Reconfigurable Network-on-Chip for 3D Neural Network Accelerators,” in IEEE/ACM International Symposium on Network-on-Chip (NOCS), Italy, 2018.
.    N. Akbari, M. Modarressi, M. Daneshtalab, M. Loni, “A Customized Processing-in-Memory Architecture for Biological Sequence Alignment,” in the 29th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Italy, 2018.
22.    P. Lotfi-Kamran, M. Modarressi, H. Sarbazi-Azad, "NOC Characteristics of Cloud Applications", in The 19th International Symposium on Computer Architecture and Digital Systems (CADS), Iran, 2017. (Best Paper Award)
23.    E. Momenzadeh, M. Modarressi, A. Mazloumi, , and M. Dneshtalab "Parallel Forwarding for Efficient Bandwidth Utilization in Networks-on-Chip", 30th Conference on Architecture of Computing Systems (ARC), Austria, 2017.
24.    N. Akbari, M. Modarressi. "A High-Performance Network-on-Chip Topology for Neuromorphic Architectures", 15th IEEE International Conference on Embedded and Ubiquitous Computing (EUC), China, 2017.
25.    B. Dabiri, S. H. Seyedaghaei Rezaei, and M. Modarressi, "Low-power Parallel Data Processing Using Computation Reuse",  7th International Conference on Information Communication and Management, Russia, 2017.
26.    A. Seyedolhosseini, N. Masoumi, and M. Modarressi, "Performance Improvement of ZigBee Networks in Coexistence of Wi-Fi Signals", 7th International Conference on Information Communication and Management, Russia, 2017.
27.    P. Lotfi-Kamran, M. Modarressi, H. Sarbazi-Azad, "Near-Ideal Networks-on-Chip for Servers", in The 23rd IEEE Symposium on High Performance Computer Architecture (HPCA), USA, 2017.
28.    M. Azimi, M. Modarressi, "Proactive Network-on-Chip Path Setup for Message Passing Programs", in Euromicro Conference on Digital System Design (DSD), Cyprus, 2016.
29.    M. Modarressi, A. Yasoubi, Ma. Modarressi, "Low-Power Online ECG Analysis Using Neural Networks", in Euromicro Conference on Digital System Design (DSD), Cyprus, 2016.
30.    A. Rezaei, M. Daneshtalab, D. Zhao, M. Modarressi, "SAMi: Self-Aware Migration Approach for Congestion Reduction in NoC-based MCSoC", in 29th IEEE International System-on-Chip Conference (SOCC), USA, 2016.
31.    S. Sayardoost Tabrizi, I. Soltani Mohammadi, A. Mazloumi, M. Modarressi, "High Performance Hybrid-switched Network-on-Chip Using Shortcut Paths", in 24th Iranian Conference on Electrical Engineering (ICEE), Iran, 2016.
32.    S. H. Seyyedaghaei Rezaei, M. Modarressi, S. Roshanisefat, M. Daneshtalab, "A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing", in EuroMicro PDP Conference, Greece, 2016.
33.    S. H. Seyyedaghaei Rezaei, M. Modarressi, R. Yazdani, M. Daneshtalab, "Fault-Tolerant 3-D Network-on-Chip Design using Dynamic Link Sharing", in the Conference on Design, Automation and Test in Europe (DATE'16), Germany, 2016.
34.    M. Modarressi, F. Faghih, M. Modarressi, "Hardware Accelerator Protein Sequencing Applications on Reconfigurable Networks-on-Chip", in the 13th. East-West Design and Test Symposium (EWDTS), Georgia, 2015.
35.    M. Faryabi, H. Dorosti, M. Modarressi and S. M. Fakhraei, "Process Variation-Aware Approximation for Efficient Timing Management of Digital Circuits", in the 13th. East-West Design and Test Symposium (EWDTS), Georgia, 2015.
36.    A. Yasoubi, R. Hojabr, H. Takshi, M. Modarressi, M. Daneshtalab, "CuPAN-High Throughput On-chip Interconnection for Neural Networks", International Conference of Neural Information Processing (ICONIP), 2015.
37.    A Firuzan, M Modarressi, M Daneshtalab, "A Reconfigurable Network-on-Chip for Efficient Implementation of Neural Networks", in 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Germany, 2015.
38.    H. Mirhosseini, M. Sadrosadati, A. Fakhrzadehgany, M. Modarressi, and H. Sarbazi-Azad, "An Energy-Efficient Virtual Channel Power-Gating Mechanism for on-Chip Networks", in the Conference on Design, Automation and Test in Europe (DATE'15), France, 2015.
39.    A. Mazloumi, M. Modarressi, "A Hybrid Packet/Circuit-switched Router to Accelerate Memory Access in NoC-based Chip Multiprocessors", in  the Conference on Design, Automation and Test in Europe (DATE'15), France, 2015.
40.    M. Zaeemi, M. Modarressi, "An FPGA-Like Ultra Low-Power Network-On-Chip for Multicore Embedded Systems", in the 11th. FPGAWORLD Conference, Denmark, 2014.
41.    M. Modarressi, H. Sarbazi-Azad, "A Reconfigurable NoC Topology for the Dark Silicon Era", in the 11th. FPGAWORLD Conference, Denmark, 2014.
42.    M. Modarressi, H. Sarbazi-Azad, "A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era", in 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'14), Switzerland, 2014.
43.    N. Teimouri, M. Modarressi, H. Sarbazi-Azad, "Power and Performance-efficient Partial-circuits in Packet-switched Networks-on-Chip", in EuroMicro PDP, Ireland, 2013.
44.    M. Modarressi, S.H. Nikounia, A. Jahangir, "Low-power arithmetic unit for DSP applications", in International Symposium on System on Chip (SoC), Finland, 2011.
45.    M. Modarressi, H. Sarbazi-Azad, "Reconfigurable Cluster-based Networks-on-Chip for Application-specific MPSoCs", in 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'12), Netherlands, 2012.
46.    Y. Asgarieh, M. Khabbazian, M. Modarressi, H. Sarbazi-Azad, "A Game Theoretical Thermal - Aware Run - Time Task Synchronization Method for Multiprocessor Systems - on - Chip", in Euromicro Conference on Digital System Design (DSD), Turkey, 2012.
47.    R. Jabbarvand, M. Modarressi, H. Sarbazi-Azad, "A Reconfigurable Fault-Tolerant Routing Algorithm to Optimize the Network-on-Chip Performance and Latency in Presence of Intermittent and Permanent Faults", in The 29th. International Conference on Computer Design (ICCD'11), USA, Oct. 2011.
48.    M. Asadinai, M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Supporting Non-contiguous Processor Allocation in CMPs Using Virtual Point-to-point Links", in Design Automation and Test in Europe Conference (DATE'11), France, March 2011.
49.    N. Teimouri, M. Modarressi, H. Sarbazi-Azad: Energy-Optimized On-Chip Networks Using Reconfigurable Shortcut Paths, in the 23rd. Conference of Architectures for Computing Systems (ARCS'11), Italy, 2011.
50.    M. Modarressi, H. Sarbazi-Azad, A. Tavakkol, "An Efficient Dynamically Reconfigurable On-chip Network Architecture", in Design Automation conferecne (DAC'10), USA, June 2010.
51.    M. Asefi, M. Modarressi, H. Sarbazi-Azad, "A Load-balanced Routing Scheme for NoCs", in Workshop on MEMS (DMEMS'10), France, June 2010.
52.    S. Sahhaf, M. Modarressi, H. Sarbazi-Azad, "A Novel SDM-based On-chip Communication Mechanism", in The Fourth European Conference of Modern Information and Communication Technologies (ECUMICT'10), Belgium, 2010.
53.    M. Modarressi, H. Sarbazi-Azad, A. Tavakkol, "Low-power and High-Performance On-Chip Communication Using Virtual Point-to-Point Connections", in The IEEE/ACM International Symposium on Network-on-Chip (NoCS'09), USA, May 2009.
54.    M. Modarressi, H. Sarbazi-Azad, M. Arjomand, "An SDM-Based Hybrid Packet-Circuit-Switched On-Chip Network", in Design, Automation, and Test in Europe Conference (DATE'09), France, Apr.2009.
55.    R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, " The 2D DBM: An Attractive Alternative to the Simple 2D Mesh Topology for On-Chip Networks", in the 26th. International Conference on Computer Design (ICCD'08), USA, Oct. 2008.
56.    R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, "A Novel High-Performance and Low-Power Mesh-Based NoC", in the 7th. IPDPS Workshop on Performance Modeling, Evaluation, and Optimization of Ubiquitous Computing and Networked Systems (IPDPS'08 PMEO), USA, 2008.
57.    M. Modarressi, H. Sarbazi-Azad, "Virtual Point-to-Point Links in Packet-Switched NoCs", IEEE International Symposium on VLSI (ISVLSI), 2008.
58.    M. Modarressi, H. Sarbazi-Azad, "Power-Aware Mapping for Reconfigurable NoC Architectures", in The 25th. International Conference on Computer Design (ICCD'07), USA, Oct. 2007.
59.    S. Hessabi, M. Modarressi, M. Goudarzi, H. Javan-Hemmat, "A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems", in International Conference on Embedded Computing Systems: Architectures, Modeling, and Simulation (IC-SAMOS VI), Greece, Jul. 2006.
60.    M. Modarressi, S. Hessabi, M. Goudarzi, "A Reconfigurable Cache Architecture for Object-Oriented Application-Specific Processors", in Canadian Conference on Electrical and Computer Engineering (CCECE'06), Canada, May 2006.
61.    M. Modarressi, H. Javan-Hemmat, S.G. Miremadi, S. Hessabi, M. Najafvand, M. Goudarzi, M. Mohamadzadeh, "A Fault-Tolerant Approach to Embedded-System Design Using Software Standby Sparing", in The 11th. International CSI Computer Conference (CSICC'06), Iran, Feb. 2006.
62.    M. Modarressi, S. Hessabi, M. Goudarzi, "A Data Prefetching Mechanism for Object-Oriented Embedded Systems Using Run-Time Profiling", in The Third IEEE Symposium on Electronic Design, Test, and Applications (DELTA'06), Malaysia, Jan. 2006.
63.    M. Modarresi, H. Sarbazi-Azad, "Parallel 3-Dimensional DCT Computation on k-Ary n-Cubes ", in The 8th International Conference on High Performance Computing in Asia Pacific Region (HPC-Asia 2005), China, Nov. 2005.
64.    M. Modarressi, M. Goudarzi, S. Hessabi: Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance. Asia-Pacific Computer Systems Architecture Conference (ACSAC'05) Singapore, 2005.

Other
65.    M. Daneshtalab, P. Liljeberg, M. Modarressi, and L. Soreas, Editorial, Special issue on network-based many-core embedded systems, Elsevier Journal of System Architecture, 2013.
66.    M. Modarressi, "High-performance and Low-power Reconfigurable NoC Topology", in DATE'09 PhD Forum, France, 2009.
67.    M. Modarressi, "An Efficient Dynamically Reconfigurable On-chip Network Architecture", in ACM Student Research Competition at PACT (ACM SRC), Austria, 2010.  (Silver Medal)
Mehdi Modarressi
Assistant Professor,
and Director of Parallel and Network-based Processing Research Laboratory,
Department of Electrical and Computer Engineering,
University of Tehran, Tehran, Iran.
Email: modarressi((at))ut.ac.ir